Workshop Intel-Danysoft | EURO-PAR 2024

Workshop Intel-Danysoft: Exploring Performance in RISC-V Vector Architecture: A Preliminary Study Integrating RISC-V and SYCL

Tuesday, August 27

Intel-Danysoft’s HPC workshop will be taught by two of Intel’s leading platform experts. Carlos García Sanchez, professor at the UCM and Victor Pérez, from the software engineering staff of Codeplay.

«This paper presents a preliminary study that evaluates the initial development board supporting the stable RISC-V Vector-1.0 ISA, with a specific focus on the integration of RISC-V and SYCL technologies. This research utilizes the SYCL-Bench benchmark suite to assess a SYCL implementation based on both clang and gcc compilers. Meanwhile gcc lacks autovectorization support for RISC-V, clang exhibits poor speedups. Significantly, a code refactor in a contemporary SYCL-style led to improved performance, achieving nearly 77% of the peak speedup compared to the auto-vectorized counterparts.»

  • Slot 9:00 – 10:00 horas.

    Introduction to oneAPI and Intel Developer Cloud infrastructure:

    • Motivation and oneAPI Standardization
    • Intel’s oneAPI Toolkits Portfolio and Components

    Introduction to SYCL

    • Introduction to SYCL2020
    • SYCL features
    • Device selection and queue concepts

  • Slot 10:30 - 12:30 horas.

    Exploring SYCL on Intel DevCloud:

    • Intel® Tiber™ Developer Cloud
    • Hardware and Software in Intel® Tiber™ Cloud
    • Hands-on Introduction to SYCL
    • Memory Model (I): Buffers & Accessors
    • Memory Model (II): USM
    • Expressing Parallelism in SYCL

    Targeting SYCL on NVIDIA and AMD devices with oneAPI

    • Bringing oneAPI to NVIDIA and AMD GPUs
    • Demo
    • Installing the plugins
    • Compiling phase

  • Slot 13:30 – 15:00 horas.

    Porting CUDA to SYCL through SYCLomatic:

    • Automatic migration of CUDA codes to SYCL
    • Hands-on migration a single source code
    • Hands-on migration for multifile source code

    Hands-on SYCL

    • Image processing example

Details:

Schedule:

8:30 Registration.
9:00 Workshop.
10:00 Rest and Coffee.
10:30 Workshop.
12:30 Lunch.
13:30 Workshop.
15:00 Closing.

Place:

The conference will take place at the Universidad Carlos III de Madrid (Madrid-Puerta de Toledo campus) 
Address: Calle Ronda de Toledo, 1 – 28005 Madrid. 

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